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1 p i 6 c 49115 0 4 d2 block diagram 2 clka[0:1] clkb[0:1] clk_sel m_reset ref_in1- ref_in1+ ref_in0+ 2 d le q 1 2 clkb[0:1]# clka[0:1]# clk_en ref_in0- 0 1 description pi6c4911504d2 is a high performance diferential bufer with divide by 2 capability. tere are also 2 selectable muxed inputs. tis device is ideal for systems that need to distribute low jitter clock signals to multiple destinations with a change from the input frequency. features ? ? 2 pairs of selectable diferential inputs ? ? 2 divide by 2 diferential lvpecl outputs and 2 bufered outputs ? ? maximum operating frequency: 650mhz ? ? rms additive jitter @ 156.25mhz (12khz C 20mhz): 30fs (typical) ? ? output skew: 60ps ? ? part to part skew: 200ps ? ? operating voltage of 2.5v and 3.3v ? ? industrial operating temperature ? ? available in lead-free package applications ? ? networking: 10gbe, 25gbe, 40gbe and 100gbe applications ? ? telecom: basestations and access points lvpecl clock buffer with 2 feature www.pericom.com pi6c491 1504d2 rev d 07/23/15 15-0101
2 pinout table pin no. pin name i/o ty pe description 1 v ee power negative supply pin 2 clk_en input pull up synchronous clock enable. when high, clock outputs follow ref_ in. when low, clk outputs are forced low, clk# are forced high 3 clk_sel input pull-down clock select input. when high, selects ref_in1. when low, selects ref_in0. 4 ref_in0+ input pull-down reference input 0 5 ref_in0- input pull up inverted reference input 0 6 r ef_in1+ input pull-down reference input 1 7 ref_in1- input pull up inverted reference input 1 8 nc - - no connect 9 m_reset input pull-down master reset pin. active high. when logic high, clkan and clkbn go low and clkan# and clkbn# go high. when logic low, outputs are enabled. 10 v dd power core power supply 11 clkb1# output diferential output, lvpecl signalling level 12 clkb1 output - diferential output, lvpecl signalling level 13, 18 v ddo power output power supply 14 clkb0# output - diferential output, lvpecl signalling level 15 clkb0 output diferential output, lvpecl signalling level 16 clka1# output diferential output, lvpecl signalling level 17 clka1 output diferential output, lvpecl signalling level 19 clka0# output diferential output, lvpecl signalling level 20 clka0 output diferential output, lvpecl signalling level pin confguration 1 2 3 ref_in0+ 4 ref_in0- 5 clk_sel 6 ref_in1- 7 clkb1 8 ref_in1+ clka0 vddo clka1 clkb0 clkb0# nc 20 19 18 17 16 15 14 13 vee clk_en clka1# clka0# clkb1# 9 m_reset 12 10vdd 11 vddo www.pericom.com pi6c491 1504d2 rev d 07/23/15 p i 6 c 49115 0 4 d2 lvpecl clock buffer with 2 feature 15-0101
3 pin characteristics symbol parameter min ty p max units c in input capacitance 4 pf r pullup input pullup resistor 51 k r pulldown input pulldown resistor 51 k control inputs inputs outputs m_reset clk_en clk_sel source clka0, clka1, clkb0, clkb1 clka0#, clka1#, clkb0#, clkb1# 1 x x x low high 0 0 0 ref_in0, ref_in0# disabled, low, disabled, high 0 0 1 ref_in1, ref_in1# disabled, low, disabled, high 0 1 0 ref_in0, ref_in0# enabled enabled 0 1 1 ref_in1, ref_in1# enabled enabled enabled disabled ref_in[0:1]+ ref_in[0:1]- clk_en clka[0:1]# clka[0:1] clkb[0:1]# clkb[0:1] clk_en timing diagram www.pericom.com pi6c491 1504d2 rev d 07/23/15 p i 6 c 49115 0 4 d2 lvpecl clock buffer with 2 feature 15-0101
4 maximum ratings (over operating free-air temperature range) note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. tis is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may afect reliability. storage temperature .............................................. -65oc to+155oc ambient temperature with power applied ......... -40oc to+85oc supply voltage (relative to vee) ............................... -0.5 to +3.7v esd protection (hbm) ......................................................... 2000v dc electrical characteristics power supply dc characterisitcs, (t a = -40oc to 85oc) symbol parameter condition min ty p max units v dd core supply voltage 3.0 3.3 3.6 v 2.375 2.5 2.625 v ddo output supply voltage 3.0 3.3 3.6 v 2.375 2.5 2.625 i ee power supply current 115 ma i dd power supply current 100 ma lvcmos/lvttl dc characteristics, (t a = -40oc to 85oc) symbol parameter condition min ty p max units v ih input high voltage v dd = 3.3 v +/- 10% 2 3.765 v v dd = 2.5 v +/- 5% 1.7 v dd + 0.3 v v il input low voltage v dd = 3.3 v +/- 10% -0.3 0.8 v v dd = 2.5 v +/- 5% -0.3 0.7 v i ih input high current clk_en v dd = vin = 3.63v 30 a m_reset, in_sel, ref_in v dd = vin = 3.63v 150 i il input low current clk_en v dd = 3.63v, v in = 0v -150 a m_reset, in_sel, ref_in v dd = 3.63v, v in = 0v -30 www.pericom.com pi6c491 1504d2 rev d 07/23/15 p i 6 c 49115 0 4 d2 lvpecl clock buffer with 2 feature 15-0101
5 differential input dc characteristics (t a = -40c to 85c) symbols parameters test conditions min. typ max. units i ih input high current ref_in- v dd = v in =3.465v 5 ua ref_in+ v dd = v in =3.465v 150 i il input low current ref_in- v dd = 3.465v or 2.625v v in = 0v -150 ua ref_in+ -5 ua v pp peak-to-peak input voltage (1) v dd = 3.3v 0.15 1.3 v v dd = 2.5v 0.25 1.3 v cmr common mode input voltage (1,2) v dd = 3.3v and 2.5v v ee + 0.5 v dd - 0.85 v notes: 1. for single ended applications, v i h = v dd + 0.3v. 2. common mode voltage is defned as v ih . lvpecl output dc characterisitcs, (t a = -40oc to 85oc) symbol parameter condition min ty p max units v oh output high voltage (1) v ddo = 3.3v 1.9 2.4 v v ddo = 2.5v 1.5 1.7 v ol output low voltage (1) v ddo = 3.3v 1.3 1.8 v v ddo = 2.5v 0.8 1.1 note: 1. lvpecl termination: source 150ohm to gnd and 100ohm across clk and clk#. www.pericom.com pi6c491 1504d2 rev d 07/23/15 p i 6 c 49115 0 4 d2 lvpecl clock buffer with 2 feature 15-0101
6 ac electrical characteristics, (t a = -40oc to 85oc) under the test confgurations shown in fgures symbol parameter condition min. ty p. max units f out output frequency 650 mhz t r / t f output rise/fall time 20% to 80%, 3.3v operation, 312.5mhz 200 700 ps 20% to 80%, 2.5v operation, 312.5mhz 160 700 ps t sk(o) output skew outputs at the same loading, same bank @ 156.25mhz 65 ps t pd propagation delay from diferential input to the diferential output cross point, clka 0.8 2.0 ns t jit(a?) additive phase jitter, (random) (1) 156.25mhz, (12khz - 20mhz) 30 fs 312.5mhz, (12khz - 20mhz) 30 fs o dc output duty cycle measured at 156.25mhz 48 50 52 % v pp output swing lvpecl outputs, single-ended, 3.3v operation 0.55 1.1 v lvpecl outputs, single-ended, 2.5v operation 0.5 0.75 note: 1. please refer to the phase noise plots. www.pericom.com pi6c491 1504d2 rev d 07/23/15 p i 6 c 49115 0 4 d2 lvpecl clock buffer with 2 feature 15-0101
7 propagation delay and output skew ref_in+ ref_in- t pdn v oh v ol clkn/ clkn# propagation delay t pd output skew t sk(o) clkn+1/ clkn+1# t pdn+1 t sk(o) t pdn+1 t sk(o) t pdn v oh v ol v oh v ol t sk(o) = t pdn+1 - t pdn part to part skew ref_in+ ref_in- t pd1 v oh v ol part1 clk/clk# part-to-part skew t sk(p) part2 clk/clk# t pd2 t sk t pd2 t sk t pd1 v oh v ol v oh v ol t sk(p) = t pd2 - t pd1 t pw clkn/ clkn# duty cycle o dc t period v oh v ol o dc = ( t pw / t period ) x 100% output duty cycle www.pericom.com pi6c491 1504d2 rev d 07/23/15 p i 6 c 49115 0 4 d2 lvpecl clock buffer with 2 feature 15-0101
8 phase noise plots f out = 156.25mhz output phase noise (dark blue) vs input phase noise (light blue) additive jitter is calculated at 156.25mhz~23fs rms (12khz to 20mhz). additive jitter = (output jitter 2 - input jitter 2 ) www.pericom.com pi6c491 1504d2 rev d 07/23/15 p i 6 c 49115 0 4 d2 lvpecl clock buffer with 2 feature 15-0101
9 lvpecl test circuit 100 z = 50 o z = 50 o 150 150 lvpec l buff er v ddox l = 0 ~ 10 in. www.pericom.com pi6c491 1504d2 rev d 07/23/15 p i 6 c 49115 0 4 d2 lvpecl clock buffer with 2 feature 15-0101
10 application information power supply filtering techniques as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter perfor - mance, power supply isolation is required. te pi6c4911504d2 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v dd , v dda and v ddo should be individually connected to the power supply plane through vias, and 0.1f bypass capacitors should be used for each pin. figure below illustrates this for a generic v dd pin and also shows that v dda requires that an additional 10 resistor along with a 10f bypass capacitor be connected to the v dda pin. v dd 0.1f 0.1f 10f 10? * 3.3v or 2.5v v dda * if v dd is 2.5v, the resistor value will be dierent, see app note for details wiring the diferential input to accept single ended levels figure 1 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v dd /2 is gener - ated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio of r1 and r2 might need to be adjusted to postion the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v dd = 3.3v, v_ref should be 1.25v and r1/r2 = 0.609. figure 1. single-ended input to dif ferential input device single ended clock input v dd r1 1k r2 1k c1 0.1 clk /clk www.pericom.com pi6c491 1504d2 rev d 07/23/15 p i 6 c 49115 0 4 d2 lvpecl clock buffer with 2 feature 15-0101
11 recommendations for unused input and output pins inputs: cref_in input: for applications not requiring the use of the clock, it can be lef foating. a 1k resistor tied from the ref_in to ground can provide additional protection. lvcmos control pins: all control pins have internal pulldowns; a 1k resistor tied from each control pin to ground can provide additional protection. outputs: lvpecl outputs: all unused lvpecl outputs can be lef foating. we recommend that there is no trace attached. both sides of the diferential output pair should either be lef foating or terminated. www.pericom.com pi6c491 1504d2 rev d 07/23/15 p i 6 c 49115 0 4 d2 lvpecl clock buffer with 2 feature 15-0101
12 lvpecl driver rpd qan+/ qbn+ lvpecl receiver vddo rpu 100 differential vddo rpu rpd qan-/ qbn- rpu rpd vddo 3.3v 2.5v 120 250 82 62.5 0.1f 0.1f rt 160 91 rt rt cmos clock 50 0.1f 0.1f 0.1f 50 rs differential clock input lvpecl driver 100 differential rpd qan+/ qbn+ lvpecl receiver vddo rpu vddo rpu rpd qan-/ qbn- rpu rpd vddo 3.3v 2.5v 120 250 82 62.5 single ended input, ac couple single ended input, dc couple lvpecl, ac couple, thevenin equivalent lvpecl, dc couple, thevenin equivalent lvpecl driver 50 qan+/ qbn+ vddo - 2v qan-/ qbn- rpu rpd vddo 3.3v 2.5v 120 250 82 62.5 vddo rpd rpu rpu rpd lvpecl driver 50 qan+/ qbn+ vddo - 2v 50 qan-/ qbn- 50 vddo - 2v single ended lvpecl, dc couple single ended lvpecl, dc couple, thevenin equivalent www.pericom.com pi6c491 1504d2 rev d 07/23/15 p i 6 c 49115 0 4 d2 lvpecl clock buffer with 2 feature 15-0101
13 thermal information symbol description condition q ja junction-to-ambient thermal resistance still air 84.0 o c/w q jc junction-to-case thermal resistance 17.0 o c/w lvpecl driver 50 qan+/ qbn+ qan-/ qbn- rt vddo 3.3v 2.5v 160 91 rt rt 50 50 0.1f 0.1f load single ended lvpecl, ac couple, thevenin equivalent www.pericom.com pi6c491 1504d2 rev d 07/23/15 p i 6 c 49115 0 4 d2 lvpecl clock buffer with 2 feature 15-0101
14 ordering information ordering code packaging type package description operating temperature pi6c4911504d2lie l pb-free & green, 20-pin tssop industrial PI6C4911504D2LIEX l pb-free & green, 20-pin tssop, tape & reel industrial notes: ? termal characteristics can be found on the company web site at www.pericom.com/packaging/ ? "e" denotes pb-free and green ? adding an "x" at the end of the ordering code denotes tape and reel packaging pericom semiconductor corporation ? 1-800-435-2336 ? www .pericom.com packaging mechanical: 20-contact tssop (l) date: 05/03/12 description: 20-pin, 173mil wide tssop package code: l document control #: pd-1311 revision: f notes: 1. refer jedec mo-153f/ac 2. controlling dimensions in millimeters 3. package outline exclusive of mold flash and metal burr 12-0373 www.pericom.com pi6c491 1504d2 rev d 07/23/15 p i 6 c 49115 0 4 d2 lvpecl clock buffer with 2 feature 15-0101

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